Processing units execute instructions to read, manipulate, and write data. Both the instructions and data are commonly stored in a separate memory, which is coupled to the processing unit via a communication channel, or memory channel. Memory controller logic integrated with the processing unit or on a separate integrated circuit (IC) manages the flow of instructions and data between the processing unit and memory. In a common example, a typical personal computer includes a central processing unit (CPU), a quantity of dynamic, random-access memory (DRAM), and a memory controller IC that manages the flow of information between the CPU and DRAM.
The speed with which a processing unit can execute instructions is limited by the speed with which it can communicate with the memory. This communication speed is limited by (1) the “interface speed,” which is a measure of how fast the information can be passed to and from the memory; and (2) the memory's “core speed,” or how quickly the memory can write and read information responsive to instructions from the memory controller.
Interface speeds have improved far more rapidly than DRAM core speeds. As a consequence, DRAM core speeds have become a limiting factor in further improvements in speed performance. To address this bottleneck, new generations of DRAM devices simply read or write more information for each memory access. If the interface speed were to double without a commensurate improvement in core performance, for example, one might simply double the amount of information read or written for each memory access (i.e., double the “access granularity”).
Unfortunately, certain classes of applications do not require high access granularity. DRAMs thus tend to access more information than is needed, which wastes power and reduces speed/performance. Energy efficiency and speed performance are design concerns in all forms of computing devices.
One solution to increasing memory access granularity is called “threading.” This technique permits a single, relatively wide memory channel to be divided into two or more sub-channels that convey relatively narrow memory “threads.” Memory threading reduces access granularity while maintaining or increasing access speeds, and in doing so reduces power consumption. Incompatibility with older “legacy” memory controllers and memory devices may slow the adoption of this important technology.